Lower-cost, more reliable, faster and higher-density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size. At present, advanced packaging methods include Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package(FOWLP), Flip Chip (Flip Chip), Package on Package (POP), and so on.
Fan-out wafer level packaging is an embedded chip packaging method based on wafer level processing, and it is one of the advanced packaging methods with more input/output (I/O) ports and better integration flexibility. Fan-out wafer level packaging has the following unique advantages compared with conventional wafer level packaging: 1) I/O spacing is flexible, which is independent of chip size; 2) only effective dies are used and the product yield can be improved; 3) having flexible3D packaging path, that is, patterns in any array can be formed at the top part; 4) having better electrical performance and thermal performance; 5) high frequency application; and 6) it is easy to achieve high-density wiring in a redistribution layer (RDL).
At present, a fan-out wafer level packaging method of radio frequency chips generally comprises the following steps: providing a carrier and forming a release layer on a surface of the carrier; photo-etching and electroplating on the adhesive layer to obtain a redistribution layer (RDL); mounting the radio frequency chip on the redistribution layer by adopting a chip bonding process; packaging the chip in a plastic packaging material layer by adopting an injection molding process; removing the carrier and the release layer; photo-etching and electroplating on the redistribution layer to form an Under-Bump Metal (UBM) layer; performing ball placement and reflow on the UBM layer to form a solder ball bump; and then performing wafer bonding and dicing. To achieve better communication effects, antennas are provided when the radio frequency chip is used, and for the existing antennas, antennas are directly laid out on a PCB or interfaces for connecting external antennas are left by developers when layout design is performed for radio frequency function modules; however, due to inconvenience in connecting the external antennas, most of the existing radio frequency antennas are directly laid out on the PCB, and in order to ensure the antenna gain, this will inevitably be at the expense of sacrificing the PCB area.
In view of this, it is necessary to design a new fan-out antenna packaging structure and a method making the same to solve the above-mentioned technical problems.